1. Field of the Invention
The invention relates to a timing reference circuit for bitline precharge for random access memory arrays such as dynamic random access memory, DRAM, arrays. The invention provides a high voltage at the gates of isolation metal oxide semiconductor field effect transistors, MOSFETs, during the period of time the bitlines and inverse bitlines are being precharged. The voltage at the gates of the isolation MOSFETs is automatically returned to a lower level when the precharge of the bitlines and inverse bitlines is complete.
2. Description of Related Art
The memory cycle of memory arrays using MOSFET technology is divided into an active period and an inactive period. At the beginning of the active period the bitlines and inverse bitlines of the memory array must be precharged to an initial voltage level. During the active period the memory cells are accessed and the bitline goes to a high voltage level and the inverse bitline goes to a low voltage level or the bitline goes to a low voltage level and the inverse bitline goes to a high voltage level depending on the initial state of the cell. During the inactive period of the memory cycle the bitline and the inverse bitline must be precharged back to the initial voltage level in preparation for the next active period.
The bitline and inverse bitline are precharged with current flowing through isolation MOSFETs. Conventional methods provide means to raise the voltage at the gates of the isolation MOSFETs during the active period of the memory cycle and returning this voltage to a lower level during the inactive period of the memory cycle, but this does not help reduce the time required to precharge the bitline and inverse bitline.
This invention provides circuits and a method of maintaining the higher voltage at the gates of the isolation MOSFETs during the precharge period and returning the voltage to a lower level before the end of the inactive period, thereby reducing the precharge time.